Rock Zhang
I am a master's student in Computer Engineering at Carnegie Mellon University, specializing in computer architecture and security. I am currently a research assistant working with
Professors Franz Franchetti and
James C. Hoe on accelerating
BGV fully homomorphic encryption on the
AMD Alveo V80 FPGA.
I received my Bachelor of Science in Computer Engineering
with Highest Distinction from Purdue University - West Lafayette.
My research interests include FPGA-based system design and hardware security. I am passionate about mathematics and enjoy learning new ideas and technologies. I am always happy to collaborate with other students.
- Interests Computer Architecture, Computer Security, Mathematics
Academic
Purdue University - West Lafayette
GPA: 4.00/4.00 | Honors: Dean's List and Semester Honors
University of Rochester
Dual-Core RISC-V Processor with Coherent Caches
- Designed a pipelined dual-core RISC-V processor with data forwarding, hazard detection, and a 2-bit branch predictor to reduce misprediction flushes and improve IPC.
- Built instruction and data caches and a cache-coherent memory controller that guarantees write atomicity across cores; implemented LR/SC atomic instructions to support locking.
- Verified the shared-memory multicore system through RTL simulation and gate-level synthesis, and prototyped it on an Intel Altera DE2 FPGA board with Quartus.
USB 1.1 Transmitter with AHB-Lite Interface
- Designed and verified a transmitter that converts AHB-Lite input into D+/D− signaling for ACK, NACK, STALL, DATA0, and DATA1 packets through a 64-byte FIFO buffer.
- Integrated it with a USB receiver into a complete USB 1.1 design.
APB-Slave UART Receiver SoC Peripheral
- Designed a UART receiver supporting 5/7/8-bit data frames with parity checking and framing and overrun error detection, exposed to the SoC as an AMBA APB slave with separate address and data phases.
Undergraduate Coursework
Computer Design and Prototyping, ASIC Design Lab, Microprocessor Systems and Interfacing, Digital System Design, Computer Security, Data Structures, Artificial Intelligence, Data Mining, Probabilistic Methods, Signals and Systems, Discrete Mathematics
Languages
SystemVerilog, RISC-V Assembly, C, Python, MATLAB, Java, C#
EDA Tools
AMD Vivado, Intel Quartus
Hardware
AMD Alveo V80, Zynq, and Artix-7 FPGAs; Intel Altera DE2 FPGA; STM32F091 MCU
Research
FPGA Acceleration of BGV Fully Homomorphic Encryption
Supervised by Professors Franz Franchetti and James C. Hoe.
Accelerator Architecture
Designed the overall BGV accelerator architecture on the AMD Alveo V80 FPGA, comprising a memory subsystem and a multi-lane compute subsystem in which parallel lanes process different RNS primes.
NTT Engine
Implemented a number theoretic transform (NTT) engine based on the Pease (constant-geometry) dataflow, with a unified butterfly unit that performs the forward NTT in DIT form and the inverse NTT in DIF form.
Key and Modulus Switching
Implemented BGV key switching and modulus switching in hardware, enabling homomorphic addition and multiplication on the FPGA.
Highlights
Research on FPGA-Accelerated Homomorphic Encryption
Began working as a research assistant with Professors Franz Franchetti and James C. Hoe at CMU, building a BGV fully homomorphic encryption accelerator on the AMD Alveo V80 FPGA.
Graduated from Purdue, Started at CMU
Received a B.S. in Computer Engineering from Purdue University with Highest Distinction and a 4.00/4.00 GPA, then began the M.S. in Computer Engineering at Carnegie Mellon University.
Dual-Core RISC-V Processor and SoC Peripherals
Designed a pipelined dual-core RISC-V processor with coherent caches, prototyped on an Intel Altera DE2 FPGA, along with a USB 1.1 transmitter and an APB-slave UART receiver in SystemVerilog.